Dual DA954D User Manual

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Summary of Contents

Page 1 - October 30

DisplayPort Physical Layer Measurements Simple steps to follow for success! Brian Fetz October 30th, 2012

Page 2

December 6, 2012 10  Ch 1 Maximize scale display, Trigger on Channel 1 Measure tCh1-Ch2 , tCh1-Ch3 , tCh1-Ch4 Ch 2, 3, 4 Preparing for Test Osci

Page 3 - Sink Device

December 6, 2012 11  Ch3 Ch1 For Level: Trigger on pattern or pulse or edge Average mode Measure Level… Vpeak to peak For Jitter: Pattern set to clo

Page 4 - AUX Channel Control

Cables: low loss and phase matched. Test Point Adapter functions to consider: • Signal Access for high speed lanes • AUX Channel lane access for con

Page 5 - DP Compliance Test Process

December 6, 2012 13  Agilent:  Standard: W2641B  Wilder:  Standard: DP-TPA-P  Mini DP: Mini-DP-TPA-P  eDP: eDP-TPA-PRC  Aux channel: DPI-TPA-A

Page 6

The Test Regimen will require control of your source device: • Bit Rate 1.62, 2.7, 5.4 Gbs • Level Settings 0, 1, 2, 3 • Pre-Emphasis

Page 7

Preparing for Test Control of your DisplayPort Device Agilent DisplayPort Test Application Set up your device

Page 8

Start at RBR (1.62Gbs) at Level setting 0 (400mV nominal) and PreEmphasis Setting 0 (0 dB nominal). D10.2 Pattern. Set Time scale to 616 ps per divis

Page 9

1 Examining Level Control Edge trigger on clock pattern Average. Set vertical to peak value at Level 0 Examining PreEmphasis and Pattern Control Puls

Page 10 - Preparing for Test

Examining Pattern Control Preparing for Test Verifying Control of your DisplayPort device 5.4Gbs pattern, Level 0(400mV nominal), PreEmphasis setting

Page 11

December 6, 2012 19 Preparing for Test Check/Analyze your signals Differential signals. One is L0+ the other is L0- They should be equal and opposite

Page 12

Topics Overview of DisplayPort Interface and Key points that affect test Quick Review of the Compliance Process Preparing for test:  Validate/Chec

Page 13

DisplayPort TX Testing

Page 14

DisplayPort TX Testing Two Specifications in play at this time: Standard DisplayPort eDP 1.3 New specs just released: (CTS in draft) eDP 1.4 MyDP

Page 15

DisplayPort Tests and Patterns December 6, 2012 22 Test RBR HBR HBR2 3-1 Eye Diagram PRBS7 PRBS7/ CP2520 CP2520 3-2 Non PreEmphasis Level PRBS7 PRBS7

Page 16

DisplayPort Tests and Levels&Pre-Emphasis December 6, 2012 23 Test Levels Pre-Emphasis 3-1 Eye Diagram RBR/HBR: Setting 2 HBR2: User Choice RBR/H

Page 17

Know that there are many test conditions! Eye Diagram: One Level, One P-E setting, 2 SSC states, 4 Lanes, 3 bit rates, two cable conditions for HBR2:

Page 18

Test Details: Screen Shots and Discussion December 6, 2012 25 General Notes: 1. DP 1.2b testing does not change testing for RBR and HBR 2. DP 1.2 te

Page 19

Test Details: Screen Shots and Discussion Eye Diagram Test: Notes: 1. RBR/HBR have fixed Mask. 2. HBR2 mask to support BER of 10-9. It is a 4 poin

Page 20 - DisplayPort TX Testing

Test Details: Screen Shots and Discussion Non-Pre-emphasized Level Test Notes: 1. The nominal settings of Level 0, 1, 2, 3 are 400, 600, 800, and 120

Page 21

Test Details: Screen Shots and Discussion December 6, 2012 28 Pre Emphasis Tests Notes: 1. The nominal settings of Level 0, 1, 2, 3 are 0, 3.5, 6, an

Page 22 - CP2520/D10.2

Test Details: Screen Shots and Discussion Skew Notes: 1. Adjacent Lanes are offset in time by 20 unit intervals. 2. Requires a longish pattern for tim

Page 23 - Pre-Emphasis

Two Interfaces Main Link 1, 2, or 4 differential lanes 3 possible bit rates (1.62Gbs, 2.7Gbs, 5.4Gbs) 4 possible level settings (400, 600, 800,120

Page 24 - Pre-Emphasis Tests:

Test Details: Screen Shots and Discussion Frequency/SSC Tests Notes: 1. Evaluate Data Rate Trend, filter data with smoothing function 2. Downspread Ra

Page 25 - DC Gain

Test Details: Screen Shots and Discussion Jitter Tests Notes: 1. RBR/HBR unchanged from DP 1.1a. Total Jitter and non-ISI Jitter. 2. HBR2 with cabl

Page 26 - Notes:

Test Details: Measurement Screen Shots and Discussion Dual Mode Tests Notes: 1. 4 lane DP device sends out HDMI content 2. Is not biased (pulled up to

Page 27 - Level setting 0

AUX Channel Testing December 6, 2012 33 Schematic

Page 28 - 179/192 = .93

AUX Channel Testing December 6, 2012 34 Test Condition of Test 8-1 AUX Channel Eye AUX Traffic 8-2 AUX Sensitivity AUX Traffic 8-3 AUX +Termination DC

Page 29 - 6.67ns / 372ps =

AUX Channel Testing December 6, 2012 35 AUX Eye Testing AUX Sensitivity A B A B Source Initiation of AUX communication Receiver Response to

Page 30 - December 6, 2012

December 6, 2012 36 DisplayPort RX Testing Notes: 1. Only one ‘test’: Stressed Receiver Test. The idea is to put in a worst case data signal (‘stress

Page 31

December 6, 2012 37 DisplayPort RX Testing Table 4.4 from DisplayPort CTS 1.2b To provide a stressed signal means:  Set up a specified minimum voltag

Page 32 - Discussion

December 6, 2012 38 DisplayPort RX Testing DisplayPort Sink Compliance Test software

Page 33 - AUX Channel Testing

Key Features • Built around the concept of Test Plan • 3 Test suites: DisplayPort Phy Layer, AUX channel, and Dual Mode. • Includes Test Selection co

Page 34

Review of DisplayPort Interface Implications for Test December 6, 2012 4 Testing Main Link There are hundreds of test conditions for DisplayPort Tx a

Page 35

Test Plans – Device Test Plan – Connection Test Plan – Selected Tests Source Tsting using DP Compliance Software Device Definition Test Connection

Page 36 - DisplayPort RX Testing

Other Considerations • Add-In your own tests • Scripts for control • Remote client Source Testing using DP Compliance Software Or save to .arsl f

Page 37

Summary Take control of your DisplayPort Testing efforts:  Understand the key attributes of the DisplayPort specification that have significan

Page 38

December 6, 2012 43 December 6, 2012 43 Additional Resources www.agilent.com/find/displayport • Agilent’s complete solution • Source compliance sof

Page 39 - Key Features

DP Compliance Test Process December 6, 2012 5 VESA has a ‘Look for the Logo’ campaign to promote consumer confidence. Each product will need to pas

Page 40 - Test Plans

Preparing for Test Check your Physical Layer Test Equipment December 6, 2012 6 Oscilloscope Level Accuracy Noise and Residual Jitter Channel to Cha

Page 41 - Other Considerations

December 6, 2012 7  Power Meter- measures dBm: dB relative to 1mW Convert with relation: 0 dBm = 1 mW = Vrms2/50 Vrms= sq

Page 42 - Summary

December 6, 2012 8  Measure Vrms in lowest scale and in the scale you will be making measurements Ch1 Ch2 Ch3 Ch4 5mV/div 438uV 431uV 429uV 418uV

Page 43 - Additional Resources

December 6, 2012 9  Adjust output on signal generator to full scale on which you will be making measurements Expected Jitter should be approximatel

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